The present disclosure relates to a nonvolatile semiconductor memory device, and more particularly to a technology of controlling a reference current.
At present, the workhorse of nonvolatile memory is flash memory. The flash memory however has problems of being large in power consumption and low in operation speed: a voltage as high as about 10 V is required to rewrite data, and the data rewrite time is of the order of microseconds or milliseconds. A circuit configuration of flash memory is disclosed in U.S. Pat. No. 5,917,753 (Patent Document 1), for example.
In recent years, development of novel nonvolatile memory devices that operate at low power and high speed is in progress. As one of nonvolatile memory devices, resistive random access memory (ReRAM) is known. The ReRAM, which achieves data rewrite of the order of nanoseconds and a voltage required for data rewrite of about 1.8 V, is operable at higher speed and lower power than flash memory.
As memory cells of the ReRAM, there are those configured as in FIGS. 14A and 14B, for example. FIG. 14A shows so-called 1T1R memory cells, where one memory cell comprises one selective transistor and one variable resistance element. FIG. 14B shows so-called cross-point memory cells, where one memory cell comprises one variable resistance element and one bidirectional diode.
The memory cell in FIG. 14A has a layout as shown in FIG. 15, for example. This memory cell has a four-layer structure, where a bit line BL is placed in a fourth layer M4 and a source line SL is placed in a first layer M1. A word line WL is a polysilicon interconnect. Since the polysilicon interconnect is high in wiring resistance and wiring capacitance, a backing interconnect WLX is provided in a second layer M2. The word line WL and the backing interconnect WLX are connected to each other at constant intervals. The interconnect layers are connected to one another through a via, and a variable resistance element RR is provided between a third layer M3 and the fourth layer M4 through the via.
Japanese Unexamined Patent Publication No. 2004-234707 (Patent Document 2) discloses a circuit configuration of ReRAM. In this ReRAM, a memory cell current is compared with a reference current by a sense amplifier, thereby determining data stored in a memory cell. In this relation, the operations of the ReRAM include read, write verify, delete verify, etc., and it is necessary to generate reference currents corresponding to these operations. Thus, a plurality of kinds of reference currents must be generated.
For example, the configuration in FIG. 4 of Patent Document 2 uses a reference cell having four circuits in each of which a fixed resistance element and a cell transistor are serially connected to each other. By selecting a desired one of the cell transistors, a reference current corresponding to the resistance value of the selected circuit is generated. As the fixed resistance elements of the reference cell, used generally are polysilicon resistance elements as shown in Wataru Otsuka et al., “A 4 Mb Conductive-Bridge Resistive Memory with 2.3 GB/s Read-Throughput and 216 MB/s Program Throughput,” 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2011, P210-211.